1. Field of the Invention
The present invention relates to a highly linear differential amplifying circuit.
2. Description of the Background Art
These days, amplifiers with high linearity are required in radio communication systems. Among conventional techniques for improving linearity of amplifiers, the multiple-gated transistor (MGTR) technique (Prior art 1, Korean Publication Patent No. 10-2002-0067331) is recognized as one of the effective methods for improving the linearity of a CMOS amplifier. This linearization technique is a technique in which second-order derivative terms of the entire transfer function are removed by controlling main and auxiliary transistors to have a proper size and applying a proper bias voltage to the main and auxiliary transistors, so that a third harmonic element is effectively removed. Based on the MGTR technique, a technique for improving linearity of a differential amplifier (Prior art 2, Korean Publication Patent No. 10-2006-0011742) has been proposed.
In manufacturing an amplifying circuit using such a conventional technique, a bonding wire is inevitably included at a source terminal of the amplifying circuit during the packaging process. The inductance of the bonding wire at the source node is known to become a path for the second harmonic feedback component, and consequently the linearity improvement effect of the original MGTR amplifier rapidly disappears as the operating frequency or the output power grows higher. In order to solve such a problem, a method was proposed to add an additional inductor in the form of a transformer to source terminals of the main and auxiliary transistors and controlling the phase of the second harmonics (Prior art 3, V Aparin and L. E. Larson, “Modified Derivative Superposition Method for Linearizing FET Low-Noise Amplifiers,” IEEE Tran. Microwave Theory and Techniques, vol. 53, no. 2, pp. 571-581, February 2005). Meanwhile, a method for improving linearity by adding a degeneration resistor to a source terminal (Prior art 4, J. Kim et. al., “A 2.4-GHz CMOS Driver Amplifier Based on Multiple-Gated Transistor and Resistive Source Degeneration for Mobile WiMAX,” in Proc. IEEE Asian Solid-State Circuits Conference, November 2006, pp. 255-258, Prior art 5, Korean Publication Patent No. 10-2007-0020794) was proposed in order to address the second harmonic feedback effect.
However, in the methods disclosed in the Prior arts 1 to 5, the linearity improvement effect is found to be unsatisfactory especially when the operating frequency or the output power grows higher.
This phenomenon is explained in detail below.
As disclosed in the Prior art 3, in accordance with the Prior art 1 for linearizing the main and auxiliary transistors through a proper sizing and biasing, the linearity improvement effect is often found to disappear as the operating frequency or the output power gets higher. This is because a second harmonic component generated by a transistor is fed back through an inductance element at a source terminal of the transistor and mixed with a fundamental frequency component of an input to generate a third-order intermodulation distortion signal, which is generally referred to as a “second harmonic feedback effect.”
In order to solve such a problem of the Prior art 1, it is effective to apply a linear feedback technique. Generally, if a linear feedback is applied to an amplifier, the output-referred third-order intercept point (OIP3) of the amplifier is improved by a factor of (1+T)1/2 at a low output power region, and also improved by a factor of (1+T)1/4 at a high output power region. Here, T denotes a feedback gain.
An example to which such a linear feedback technique is applied is illustrated in FIG. 1.
Referring to FIG. 1, a resistor RS with small resistance is added to a source terminal of the amplifier and then connected in series to a bonding wire having an inductance element LS so as to realize the wanted linear feedback. In such a configuration, the OIP3 of the amplifier can be enhanced as disclosed in the Prior arts 4 and 5.
Such a source degeneration resistor technique may be applied to differential amplifier topologies as shown in FIGS. 2 and 3. When a source degeneration resistor is added to a differential amplifier, source degeneration resistors can be completely shared by the differential transistor pair as shown in FIG. 2, or the source degeneration resistors of the main and auxiliary transistors can be completely separated from each other as shown in FIG. 3.
However, such conventional structures have the following problems.
First of all, the structure of FIG. 2 in which RS and LS are shared by the main and auxiliary transistors is considerably sensitive to the operating conditions of the main transistor MMT in removing a third-order derivative coefficient (93) of the total transfer function. In this structure, even though the g3 cancellation condition is achieved in DC, the condition is easily disturbed in RF operation because a rather big signal swing fed through the main transistors MMT will appear at the common source node and as a result, disturbs the biasing condition of the auxiliary transistors MAT. Therefore, in the structure in which the source degeneration resistor is shared by the main and auxiliary transistors, it is not easy to maintain the improved linearity even under the large signal operation. Also the g3 cancellation condition is sensitive to the process, temperature, and voltage variations in this shared structure, which is not desirable either.
The problems of the shared structure described above may be mitigated by separating the source degeneration resistors. As shown in FIG. 3, the separate structure allows independent optimization of the degeneration resistors RSM and RSA for the main and auxiliary transistors MMT and MAT, respectively. Here, the RSM is desirably made small to minimize the gain degradation, while the RSA is desirably made large to effectively perform the second harmonic feedback cancellation. However, another difficulty arises in this structure. When RSA becomes high, it lowers the effective g3 of the auxiliary transistor, and thus makes it difficult to maintain the g3 cancellation condition with a reasonable gate size of the auxiliary transistor. Such a difficulty often leads to an unsatisfactory linearity performance as the output power becomes high.